In the conventional push/pull AND driver of FIG. 1 consisting of the FET devices 1' to 8', the gate of the output depletion mode FET device 6' is connected through a self-biased depletion mode load device 8' to the drain potential VD in what is effectively a shorted connection to drain potential. Thus, as the output node for the circuit rises, there is no chance for any bootstrapping effect to take place through the gate-to-source capacitance, since the gate potential for the output device 6' cannot rise above the drain potential. This limits the rise time for output waveforms from the driver circuit.